Embodiments of the disclosed technology relate to a method for fabricating a thin film pattern and an array substrate.
A liquid crystal display (LCD) is a kind of flat display device which is mostly adopted at present. Thin film transistor liquid crystal displays (TFT-LCDs) are a kind of dominating products in the LCD market. The liquid crystal panel in a liquid crystal display device comprises an array substrate and a color filter substrate. The array substrate is typically configured to comprise data lines and gate lines intersecting with each other so as to form pixel units arranged in a matrix. Each of the pixel units is provided with a pixel electrode and a TFT switch element particularly comprising a gate electrode, an active layer, a source electrode and a drain electrode. The active layer generally comprises an amorphous silicon layer and an impurity-doped amorphous silicon layer. The source electrode and the drain electrode are located on the impurity-doped amorphous silicon layer of the active layer and the impurity-doped amorphous silicon layer between the source electrode and the drain electrode is etched to form a channel.
In a conventional four-mask patterning process for manufacturing an array substrate, patterns of the active layers, the source electrodes, the drain electrodes and the data lines are formed in one patterning process with a double tone mask. For meeting requirements of a large-sized liquid crystal panel in electric conducting, data lines would be better fabricated by a metal material having better electric conductive characteristics, such as one layer or layers of Aluminum (Al), Al alloy such as AlNd, Molybdenum (Mo), Mo/Al, Mo/AlNd, Mo/Al or Al alloy/Mo, Copper (Cu). Titanium (Ti), Ti/Al (AlNd)/Ti, Cu/Mo or Mo alloy. When one of these metal materials is elected, a method comprising one process of photolithography, two processes of wet etching, two processes of dry etching and two processes of ashing for removing photoresist are required to form data lines, and typical processes are as shown in FIGS. 1A to 1F.
Firstly, a semiconductor film 10, an impurity-doped semiconductor film 20 and a data line metal film 30 (other films not directly related to the process are not shown) are sequentially deposited on a base substrate 1 or other layers on the base substrate 1. Then, a photoresist layer 40 is applied onto the data line metal film 30, and the photoresist layer 40 is exposed and developed with a double tone mask, so as to form patterns comprising a totally left region, a partially left region and a totally removed region. The partially left region of the photoresist layer 40 has a thickness less than that of the totally left region. The totally left region corresponds to the positions of the data lines, the source electrodes and the drain electrodes, and the partially left region corresponds to the channels. As shown in FIG. 1A, in the region which corresponds to the positions of the data lines, after exposure and development, the totally left region of the photoresist layer 40 is formed thereon with the totally removed region located on its both sides.
Subsequently, a first wet etching is performed. That is, the data line metal film 30 located in the totally removed region of the photoresist is etched with a suitable etchant. Both sides of the data line metal film 30 are etched to be recessed with respect to the photoresist layer 40 due to the anisotropy of the etching, as shown in FIG. 1B.
Next, a first dry etching is performed. That is, the semiconductor film 10 and the impurity-doped semiconductor film 20 of the active layer located in the totally removed region are etched, as shown in FIG. 1C.
Then, an ashing process is performed so as to remove the photoresist layer 40 by a certain thickness. As a result, the photoresist layer 40 located in the partially left region is removed, and the photoresist layer 40 located in the totally left region is reduced in thickness by a certain amount. During the ashing, the photoresist layer 40 is reduced not only in the thickness direction, but also in its area due to ashing at the recessed portion of the metal film, as shown in FIG. 1D.
By a second wet etching, the data line metal film 30 in the partially left region is etched. Since both sides of the data lines are exposed, the recessed portion is further recessed, as shown in FIG. 1E.
By a second dry etching, the impurity-doped semiconductor film 20 in the partially left region is etched so as to form a channel of TFT. However, parts of the impurity-doped semiconductor film 20 located on both sides of the data lines are also exposed due to the previous ashing of the photoresist layer 40, and then are etched, as shown in FIG. 1F. On both sides of the data lines, there is remained a part of active layer, i.e., remained a part of the semiconductor film 10, with a certain thickness beyond the data lines.
The data line pattern formed through the above etching processes is shown in FIG. 1F. There are undesired portions of the active layer extending beyond both sides of the data line pattern, which results in critical dimension bias (CD bias). Therefore, the line width of the data lines is determined by the width of the remained active layer in fact. Since the metal film pattern for electric conducting practically is relatively narrow, the data lines are subject to decreased capability of electric conducting due to high-resistance. Since the capability of transmitting current of the data lines decreases, a signal transmission delay will occur with the display effect being affected disadvantageously. The design of the bonding region around the pixel region is also affected significantly and the data lines extending to the bonding region are arranged densely to connect drive lines. The amorphous silicon film on both sides of the data lines has an increased line width, so the area of the bonding region is increased correspondingly. Generally, the producers have to deal with this problem by reducing the pixel region.
Since the wet etching for the metal film can results in a recessed portion on both sides due to over-etching, and then results in the ashing of the photoresist above the recessed portion. In this case, semiconductor films are left on both sides of the data lines. However, if the metal film is etched by a dry etching process, the problems such as process complexity, corrosion and increased product cost will arise. The above problems present not only in the process for fabricating the array substrate, but also in any processes for wet etching and dry etching different films sequentially with a double tone mask.